Capture hardware
Bandwidth and timing
Instruction trace at full clock rate needs dedicated bandwidth and accurate timestamps. Control of the capture hardware gives the software reliable evidence of target behavior.
Debug and capture hardware · In development
BKPT One
A programmable debug and trace probe for everyday embedded engineering.
BreakPoint One combines flash programming, debugging, and instruction trace with configurable FPGA hardware. It is being developed to make advanced capture and measurement capabilities accessible to more engineering teams.
Open FPGA capacity and an instrument port let engineers extend the probe with custom triggers, protocol decoding, and logic capture. The same tools support visual investigation, scripts, and AI agents.
Programmable by design
Configure the probe for your bench
The instrument port connects the FPGA to external equipment. Configure trigger inputs, clock outputs, synchronization pulses, and logic analyzer lanes through software, without writing HDL or using a vendor toolchain.
Route a function trigger to an oscilloscope, or use an external edge to freeze a capture with its pre-trigger history. Events are timestamped by the same hardware clock as the instruction trace.
Every setting available in the app has a documented command, so the same configuration can run from a bench script or in CI. The probe reports its capabilities to the host tools.
- Input
- Trigger edges and logic lanes, latched at the capture clock
- Output
- Clocks, sync pulses, and patterns your bench gear can follow
- Trigger
- A function, a data value, or an external edge, in either direction
- Capture
- Arm, freeze, and pre-trigger around the event that matters
- Script
- One documented protocol shared by the app, the CLI, and CI
- Interop
- Anything with a wire and a timestamp can join
Shared capture data
One record across the tools
ViewAlyzer visualizes the capture, BKPT Studio’s agent queries it, and Assert tests against it. A documented format also makes the data available to your own scripts.
Existing equipment
Use your current probe
The BKPT software stack works with standard debug probes today. BKPT One extends the available capture capabilities; it is not required to get started.
Hardware comparison
Choosing the right probe
ST-LINK, J-Link, and J-Trace serve established needs, from development-board debugging to specialist trace and validation work. BKPT One focuses on accessible instruction trace and configurable instrumentation for the daily firmware bench.
The comparison below retains the July 2026 price and capability snapshot. BKPT One is in private beta; general-availability pricing has not been announced.
Scroll horizontally to compare all four probes.
| JULY 2026 · US LIST | STLINK-V3STMICROELECTRONICS | J-LINK BASE / PLUSSEGGER | J-TRACE PRO CORTEX-MSEGGER | BKPT OneBKPT LABS |
|---|---|---|---|---|
| PRICE | About $35 to $43, and already on the boards you own | $598 / $798 | $1,880. Whole-family model: $3,080 | Private beta. GA pricing aimed at a bench budget, not a lab one |
| TARGETS | STM32 and STM8 only | The industry catalog: thousands of devices across every vendor | M-profile cores in this model; A / R need the $3,080 one | ARM microcontroller cores first for wide market reach, more to come. Flashes 10,000+ device variants via the CMSIS-Pack FLM catalog |
| DEBUG: FLASH / HALT / STEP | Yes | Yes | Yes | Yes: it replaces the box on your desk |
| SWO: PRINTF, SAMPLING | Yes | Yes | Yes | Yes |
| INSTRUCTION TRACE (ETM/ETR/ETF) | No | No: SWO only | Yes: streaming. The reference instrument | Yes: streaming over USB-C. The reason it exists |
| TRIGGER I/O, STAMPED IN HARDWARE | Bridge GPIOs, not stamped against a capture | No external trigger pins | No external trigger pins | In and out, latched on the capture clock, with pre-trigger history |
| SPARE FABRIC FOR YOUR PROBLEM | Fixed function | Fixed function | Fixed function | Most of the FPGA is left open: triggers, clocks, logic lanes for the user to customize. Pre built ip such as LogicLite so your probe becomes much more |
| CAPTURE DATA | None: nothing to capture | None: nothing to capture | Vendor tools (Ozone) | One documented file: GUI, agent, CI, and your own scripts |
| TRACK RECORD | The default on every ST board | Two decades, every IDE | The validation-lab reference | Private beta. This row is earned; give us time |
When to choose a specialist lab instrument
- Your target is Cortex-A / R, or not ARM at all
- You need coverage evidence a certification auditor will accept
- The probe must flash anything in the building, today
- Keil or IAR integration is non-negotiable
Where BKPT One fits
- The daily question: what did my firmware actually do
- Trace as a daily habit, not a booked lab slot
- A bench where firmware, power, and external events share one clock
- Engineers who want to build their own instrumentation
J-Link and J-Trace are trademarks of SEGGER Microcontroller GmbH. ST-LINK is a trademark of STMicroelectronics. BKPT Labs is not affiliated with, or endorsed by, either company. Prices are US web-shop list prices as of July 2026; capabilities are summarized from public vendor documentation. Spot an error? Tell us and we will fix it.
Bench study · Power and trace
Current and instructions on one timeline
A Joulescope JS320 connected to the target rail records current and power. The probe timestamps synchronization edges, and a merge step brings those measurements into the instruction trace capture.
The result connects energy use to the functions that caused it. The same approach can connect other instruments and external event streams through a common timing reference.
Read the full field note
Engineering workflows
From capture to evidence
Capabilities demonstrated on the development hardware and supported by the shared capture workflow.
Energy per function
Current measurements travel with the capture, placing power data alongside execution time and cycles in the function table.
Profiling a running target
Collect program counter samples without instrumenting or halting the firmware. A probe firmware update increased our measured sampling rate from 137 to 6,866 samples per second.
Synchronized bench instruments
Hardware-timestamped trigger inputs and outputs connect external measurements to the code running on the target.
Documented capture files
The same record can be opened by ViewAlyzer, queried by BKPT Studio, tested by Assert, and read by your own scripts.
Timing checks in CI
A scriptable probe and saved capture let teams turn deadline budgets into repeatable checks on real silicon.
Structured evidence for AI agents
Agents can query the recorded target behavior directly and use the relevant evidence to investigate a problem.
Development hardware
Target specifications
Subject to change as the hardware and firmware develop.
- Interfaces
- 20 pin Cortex debug + trace · SWD / JTAG / SWO / ETM
- Record
- Instruction level, timestamped at capture
- Output
- Continuous stream to host over USB-C 3.2
- Targets
- ARM microcontroller cores first, more to come · 10,000+ device variants via CMSIS-Pack FLM
- Software
- Native across the whole BKPT stack
- Sync
- Trigger in / out, edges timestamped in hardware
- Expansion
- User assignable I/O: triggers, clocks, logic lanes, set in software
- Firmware
- Field updatable, versioned, capability reported to the host
- Status
- In development · PRIVATE BETA
Join the private beta
Receive engineering updates and help shape the hardware before general availability.